library IEEE;
use IEEE.std_logic_1164.all;

entity testbench_fsm_uart is
end testbench_fsm_uart;

architecture test of testbench_fsm_uart is

	constant PERIOD : time := 10 ns;

	component fsm_uart
		port (
			reset_i : in  std_logic := '0';
			txclk_i : in  std_logic;
			start_i : in  std_logic := '0';
			zero_i  : in  std_logic := '0';
			ti_o 	: out std_logic;
			send_o  : out std_logic;
			data_o  : out std_logic;
			mode_o  : out std_logic;
			shift_o : out std_logic
		);
	end component;

	signal reset : std_logic;
	signal txclk : std_logic;
	signal start : std_logic;
	signal zero  : std_logic;
	signal ti 	 : std_logic;
	signal send  : std_logic;
	signal data  : std_logic;
	signal mode  : std_logic;
	signal shift : std_logic;

begin

	fsm_uart_inst : fsm_uart
		port map (
			reset_i => reset,
			txclk_i => txclk,
			start_i => start,
			zero_i  => zero,
			ti_o 	=> ti,
			send_o  => send,
			data_o  => data,
			mode_o  => mode,
			shift_o => shift
		);

	gen_clk : process
	begin
		txclk <= '0';
		wait for PERIOD/2;
		txclk <= '1';
		wait for PERIOD/2;
	end process;

	gen_test : process
	begin
		wait for 5*PERIOD;

		reset <= '1';
		start <= '0';
		zero  <= '0';
		
		wait for PERIOD;

		reset <= '0';
		start <= '1';
		zero  <= '0';

		wait for PERIOD;

		start <= '0';

		wait for 6*PERIOD;

		zero  <= '1';

		wait;
	end process;

end test;
